// 控制单元
module Control_Unit (
	input  [4:0] OP,
	input   z,
	output [1:0] alub,PCsource,regdata,
	output [3:0] aluc,
	output sext,wreg,jr,wmem,rmem

);
    // wire i_L,i_S,i_ADD,i_SUB,i_LI,i_NOT,i_AND,i_OR,i_LSH,i_RSH,i_RSHU,i_J,i_JL,i_JR,i_JLR,i_BZ0,i_BZ1,i_BNZ0,i_BNZ1,i_H;

	wire i_L    = (OP == 5'b00010)? 1:0;
	wire i_S    = (OP == 5'b00011)? 1:0;
	wire i_ADD  = (OP == 5'b01000)? 1:0;
	wire i_SUB  = (OP == 5'b01001)? 1:0;
	wire i_LI   = (OP == 5'b00001)? 1:0;
	wire i_NOT  = (OP == 5'b01010)? 1:0;
	wire i_AND  = (OP == 5'b01011)? 1:0;
	wire i_OR   = (OP == 5'b01100)? 1:0;
	wire i_LSH  = (OP == 5'b01101)? 1:0;
	wire i_RSH  = (OP == 5'b01110)? 1:0;
	wire i_RSHU = (OP == 5'b01111)? 1:0;
	wire i_J    = (OP == 5'b10000)? 1:0;
	wire i_JL   = (OP == 5'b10001)? 1:0;
	wire i_JR   = (OP == 5'b10010)? 1:0;
	wire i_JLR  = (OP == 5'b10100)? 1:0;
	wire i_BZ0  = (OP == 5'b00100 & z == 1'b0)? 1:0;
	wire i_BZ1  = (OP == 5'b00100 & z == 1'b1)? 1:0;
	wire i_BNZ0 = (OP == 5'b00101 & z == 1'b0)? 1:0;
	wire i_BNZ1 = (OP == 5'b00101 & z == 1'b1)? 1:0;
	wire i_H    = (OP == 5'b11111)? 1:0;
	
	assign jr   		= i_JR + i_JLR + i_BZ0 + i_BZ1 + i_BNZ0 + i_BNZ1;
	assign sext 		= i_L + i_S + i_J + i_JL + i_JR + i_JLR + i_BZ0 + i_BZ1 + i_BNZ0 + i_BNZ1;
    assign wreg 		= i_L + i_ADD + i_SUB + i_LI + i_NOT + i_AND + i_OR + i_LSH + i_RSH + i_RSHU + i_JL;
    assign regdata[1] 	= i_JLR + i_L;
    assign regdata[0] 	= i_JL + i_L;
    assign alub[1] 		= i_S + i_LSH + i_RSH + i_RSHU + i_BZ0 + i_BZ1 + i_BNZ0 + i_BNZ1;
    assign alub[0] 		= i_L + i_LI + i_JR + i_JLR + i_BZ0 + i_BZ1 + i_BNZ0 + i_BNZ1;
    assign aluc[3] 		= i_SUB + i_BZ0 + i_BZ1 + i_BNZ0 + i_BNZ1;
    assign aluc[2] 		= i_OR + i_LSH + i_RSH + i_RSHU;
    assign aluc[1] 		= i_NOT + i_AND + i_RSH + i_RSHU;
    assign aluc[0] 		= i_LI + i_AND + i_LSH + i_RSHU;

    assign wmem 		= i_S;
    assign rmem 		= i_L;
    assign PCsource[1]  = i_JR + i_JLR;
    assign PCsource[0]  = i_J + i_JL + i_BZ1 + i_BNZ0;
    

endmodule